library verilog;
use verilog.vl_types.all;
entity top is
    port(
        speaker         : out    vl_logic;
        clk_1khz        : in     vl_logic;
        rst             : in     vl_logic;
        \mod\           : in     vl_logic;
        \select\        : in     vl_logic;
        set             : in     vl_logic;
        stop            : in     vl_logic;
        h               : out    vl_logic_vector(7 downto 0);
        m               : out    vl_logic_vector(7 downto 0);
        s               : out    vl_logic_vector(7 downto 0)
    );
end top;
